Generic bit error rate analyzer for use with serial data links
US10198331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Mar 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.