Tejinder Kumar
7Patents
1h-index
6Co-inventors
33Inventor score
Filing activity: Dec 12, 2016 → Dec 2, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10949258B1 | Multistage round robin arbitration in a multiuser system | Electricity | 2 | Active |
| US10838892B1 | Multistage round robin arbitration | Physics | 1 | Active |
| US10222415B2 | Generic width independent parallel checker for a device under test | Physics | 1 | Active |
| US10404278B2 | Parallel pipeline logic circuit for generating CRC values utilizing lookup table | Electricity | 0 | Active |
| US10198331B2 | Generic bit error rate analyzer for use with serial data links | Physics | 0 | Active |
| US10572440B2 | High operation frequency, area efficient and cost effective content addressable memory architecture | Physics | 0 | Active |
| US10302695B2 | Low area parallel checker for multiple test patterns | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.