System on chip integrity verification method and system
US10198332B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Mar 2, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/781
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for checking the integrity of a system on chip (SOC) are described. The SOC can include a controller and one or more registers. Register value(s) from the register(s) can be obtained at a first time to generate a first set of register values. Process(es) of the SOC are executed at a second time after the first time. Register values can again be obtained from the registers at a third time after the second time to generate a second set of register values. The first set of register values can be compared with the second set of register values. Based on the comparison, an operating mode of the SOC can be adjusted. The SOC integrity verification system and method can be used in safety and/or monitoring application(s), such as ASIL applications. For example, the system and method can be used in partial or fully autonomous (self-driving) automotive systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.