Test, validation, and debug architecture

US10198333B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Mark B. Trobough · Beaverton, US
• Keshavan Tiruvallur · Tigard, US
• Chinna Prudvi · Portland, US
• Christian Iovin · Federal Way, US
• David W. Grawrock · Beaverton, US
• Jay Nejedlo · Wilsonville, US
• Ashok N. Kabadi · Portland, US
• Travis K. Goff · Hillsboro, US
• Evan J. Halprin · Hillsboro, US
• Kapila B. Udawatta · Folsom, US
• Jiun Long Foo · Bayan Lepas, MY
• Wee Hoo Cheah · Bayan Lepas, MY
• Vui Yong Liew · Bukit Mertajam, MY
• Selvakumar Raja Gopal · Tapah, MY
• Yuen Tat Lee · Bayan Lepas, MY
• Samie B. Samaan · Lake Oswego, US
• Kip C. Killpack · Beaverton, US
• Neil Dobler · Beaverton, US
• Nagib Hakim · Santa Clara, US
• Brian Meyer · Cornelius, US
• William Penner · Olympia, US
• John L. Baudrexl · Olympia, US
• Russell J. Wunderlich · Livermore, US
• James J. Grealish · Beaverton, US
• Kyle Markley · Hillsboro, US
• Timothy S. Storey · Hillsboro, US
• Loren J. McConnell · Forest Grove, US
• Lyle Cool · Beaverton, US
• Mukesh Kataria · Santa Clara, US
• Rahima K. Mohammed · San Jose, US

Key dates

• Filing date: Dec 23, 2010
• Grant date: Feb 5, 2019
• Expiry date: Nov 27, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/267
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.