Jay Nejedlo
10Patents
7h-index
66Co-inventors
61Inventor score
Filing activity: Dec 16, 2002 → Dec 23, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7437643B2 | Automated BIST execution scheme for a link | Physics | 22 | Expired |
| US6826100B2 | Push button mode automatic pattern switching for interconnect built-in self test | Physics | 20 | Expired |
| US7464307B2 | High performance serial bus testing methodology | Electricity | 18 | Expired |
| US7536267B2 | Built-in self test for memory interconnect testing | Physics | 17 | Active |
| US7155370B2 | Reusable, built-in self-test methodology for computer systems | Physics | 17 | Expired |
| US7047458B2 | Testing methodology and apparatus for interconnects | Physics | 15 | Expired |
| US8868992B2 | Robust memory link testing using memory controller | Physics | 10 | Active |
| US7590504B2 | Graphical user interface for creation of IBIST tests | Physics | 7 | Active |
| US7562274B2 | User data driven test control software application the requires no software maintenance | Physics | 5 | Active |
| US10198333B2 | Test, validation, and debug architecture | Physics | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.