Systems and methods of adjusting an interface bus speed
US10198383B2 · kind B2 · utility
1Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Feb 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1039
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a first latch configured to be coupled to a bus and configured to receive a data signal and a clock signal. The device also includes a delay element configured to generate a delayed version of the data signal or a delayed version of the clock signal. A second latch is coupled to the delay element and configured to receive the delayed version of the data signal or the delayed version of the clock signal. The device further includes a comparator coupled to the first latch and the second latch. The comparator is configured to receive a first output from the first latch and a second output from the second latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.