Delamination-resistant semiconductor device and associated method
US10199333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Jul 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/026
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A delamination-resistant semiconductor device includes a conductive layer, a semiconductor layer, and a spacer. The conductive layer has a first side opposite a second side. The semiconductor layer is on the first side and defines an aperture therethrough spanned by the conductive layer. The spacer is on the second side and has a top surface, proximate the conductive layer, that defines a blind hole spanned by the conductive layer. A method for preventing delamination of a multilayer structure, includes a step of disposing a first layer on a substrate such that the first layer spans an aperture of the substrate. The method also includes a step of disposing a second layer on the first layer. The second layer has a blind hole adjacent to the first layer such that the first layer spans the blind hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.