Die sidewall interconnects for 3D chip assemblies
US10199354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Dec 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06551
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked-chip assembly including an IC chip or die that is electrically interconnected to another chip and/or a substrate by one or more traces that are coupled through sidewalls of the chip. Electrical traces extending over a sidewall of the chip may contact metal traces of one or more die interconnect levels that intersect the chip edge. Following chip fabrication, singulation may expose a metal trace that intersects the chip sidewall. Following singulation, a conductive sidewall interconnect trace formed over the chip sidewall is to couple the exposed trace to a top or bottom side of a chip or substrate. The sidewall interconnect trace may be further coupled to a ground, signal, or power rail. The sidewall interconnect trace may terminate with a bond pad to which another chip, substrate, or wire lead is bonded. The sidewall interconnect trace may terminate at another sidewall location on the same chip or another chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.