Semiconductor devices including stacked semiconductor chips
US10199355B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Nov 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldTransport
- WIPO sectorMechanical engineering
Abstract
A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.