Self-setting/resetting latch
US10200017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Aug 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-setting/resetting latch circuit is disclosed that includes resistive loads for inverters used for setting and clearing the latch. In a first embodiment, the resistive loads cause the latch circuit to automatically set in response to a power supply voltage going low. In an alternate embodiment, the latch circuit is configured to be self-resetting or self-clearing when the power supply voltage goes low by reversing the set and clear terminals of the latch circuit and selecting a different node to be the output terminal of the latch circuit. The disclosed latch circuit is small and robust and draws zero power in the set state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.