Danut Manea
20Patents
6h-index
14Co-inventors
66Inventor score
Filing activity: Jun 18, 2002 → Sep 15, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6714448B2 | Method of programming a multi-level memory device | Physics | 33 | Expired |
| US6621745B1 | Row decoder circuit for use in programming a memory device | Physics | 23 | Expired |
| US6724662B2 | Method of recovering overerased bits in a memory device | Physics | 17 | Expired |
| US6618297B1 | Method of establishing reference levels for sensing multilevel memory cell states | Physics | 14 | Expired |
| US9037890B2 | Ultra-deep power-down mode for memory devices | Emerging Cross-Sectional Technologies | 13 | Active |
| US9013231B1 | Voltage reference with low sensitivity to package shift | Physics | 8 | Active |
| US7929356B2 | Method and system to access memory | Emerging Cross-Sectional Technologies | 6 | Active |
| US7242242B2 | Fast dynamic low-voltage current mirror with compensated error | Physics | 4 | Expired |
| US9490999B2 | Single-wire communications using iterative baud learning | Emerging Cross-Sectional Technologies | 2 | Active |
| US9483108B2 | Ultra-deep power-down mode for memory devices | Emerging Cross-Sectional Technologies | 2 | Active |
| US7236050B2 | Fast dynamic low-voltage current mirror with compensated error | Physics | 1 | Expired |
| US8208315B2 | Method and system to access memory | Emerging Cross-Sectional Technologies | 1 | Active |
| US7084699B2 | Fast dynamic low-voltage current mirror with compensated error | Physics | 1 | Expired |
| US9501078B2 | Voltage reference with low sensitivty to package shift | Physics | 1 | Active |
| US9882738B2 | Single-wire communications using iterative baud learning | Emerging Cross-Sectional Technologies | 0 | Active |
| US10200017B2 | Self-setting/resetting latch | Electricity | 0 | Active |
| US8885413B2 | Adaptive programming for non-volatile memory devices | Physics | 0 | Active |
| US11024373B2 | Voltage-mode bit line precharge for random-access memory cells | Physics | 0 | Active |
| US11967374B2 | Voltage-mode bit line precharge for random-access memory cells | Physics | 0 | Active |
| US11482281B2 | Voltage-mode bit line precharge for random-access memory cells | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.