Packet descriptor storage in packet memory with cache
US10200313B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Jul 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9078
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A first memory device stores (i) a head part of a FIFO queue structured as a linked list (LL) of LL elements arranged in an order in which the LL elements were added to the FIFO queue and (ii) a tail part of the FIFO queue. A second memory device stores a middle part of the FIFO queue, the middle part comprising a LL elements following, in an order, the head part and preceding, in the order, the tail part. A queue controller retrieves LL elements in the head part from the first memory device, moves LL elements in the middle part from the second memory device to the head part in the first memory device prior to the head part becoming empty, and updates LL parameters corresponding to the moved LL elements to indicate storage of the moved LL elements changing from the second memory device to the first memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.