Dummy fin cell placement in an integrated circuit layout
US10204202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2016 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | May 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.