Inventor · Baoshan, TW

Tzung-Chi Lee

18Patents
6h-index
21Co-inventors
62Inventor score

Filing activity: Jun 30, 2006 → Aug 5, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8125051B2 Device layout for gate last process Electricity 15 Active
US10079289B2 Metal gate structure and methods thereof Electricity 10 Active
US9865589B1 System and method of fabricating ESD FinFET with improved metal landing in the drain Electricity 7 Active
US8368136B2 Integrating a capacitor in a metal gate last process Electricity 7 Active
US8237227B2 Dummy gate structure for gate last process Electricity 7 Active
US10141296B2 Dummy fin cell placement in an integrated circuit layout Electricity 6 Active
US8530326B2 Method of fabricating a dummy gate structure in a gate last process Electricity 5 Active
US10204202B2 Dummy fin cell placement in an integrated circuit layout Electricity 4 Active
US10276559B2 System and method of fabricating ESD FinFET with improved metal landing in the drain Electricity 3 Active
US10535746B2 Metal gate structure and methods thereof Electricity 2 Active
US11004842B2 System and method of fabricating ESD FinFET with improved metal landing in the drain Electricity 0 Active
US7550795B2 SOI devices and methods for fabricating the same Electricity 0 Active
US10453837B2 System and method of fabricating ESD finFET with improved metal landing in the drain Electricity 0 Active
US11881477B2 Dummy poly layout for high density devices Electricity 0 Active
US12199087B2 Dummy poly layout for high density devices Electricity 0 Active
US11043572B2 Metal gate structure and methods thereof Electricity 0 Active
US7803674B2 Methods for fabricating SOI devices Electricity 0 Active
US7812379B2 SOI devices Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.