Method and system for vertical power devices
US10204778B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2017 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Dec 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02378
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes providing an engineered substrate. The engineered substrate includes a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer. The method further includes forming a Schottky diode coupled to the engineered substrate. The Schottky diode has a top surface and a bottom surface. The bottom surface is coupled to the substantially single crystalline silicon layer. The method further includes forming a Schottky contact coupled to the top surface of the Schottky diode, forming a metal plating coupled to the Schottky contact, removing the engineered substrate to expose the bottom surface of the Schottky diode, and forming an ohmic contact on the bottom surface of the Schottky diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.