Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects
US10204830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2017 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Oct 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.