Inventor · Portland, OR, US

Elliot N. Tan

33Patents
4h-index
54Co-inventors
62Inventor score

Filing activity: Dec 31, 2007 → Oct 27, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9793159B2 Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects Electricity 13 Active
US10211088B2 Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects Electricity 9 Active
US9558947B2 Pattern decomposition lithography techniques Electricity 6 Active
US8314034B2 Feature size reduction Electricity 4 Active
US8860184B2 Spacer assisted pitch division lithography Emerging Cross-Sectional Technologies 3 Active
US10409152B2 Pattern decomposition lithography techniques Electricity 3 Active
US10892223B2 Advanced lithography and self-assembled devices Electricity 3 Active
US10204830B2 Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects Electricity 3 Active
US10490519B2 Pattern decomposition lithography techniques Electricity 2 Active
US11056492B1 Dense memory arrays utilizing access transistors with back-side contacts Electricity 2 Active
US9379010B2 Methods for forming interconnect layers having tight pitch interconnect structures Electricity 2 Active
US9659860B2 Method and structure to contact tight pitch conductive layers with guided vias Electricity 1 Active
US11139300B2 Three-dimensional memory arrays with layer selector transistors Electricity 1 Active
US7977248B2 Double patterning with single hard mask Electricity 1 Active
US11107786B2 Pattern decomposition lithography techniques Electricity 1 Active
US12080781B2 Fabrication of thin film fin transistor structure Electricity 0 Active
US11888043B2 Contact over active gate structures with conductive gate taps for advanced integrated circuit structure fabrication Electricity 0 Active
US12249541B2 Vertical edge blocking (VEB) technique for increasing patterning process margin Electricity 0 Active
US11373950B2 Advanced lithography and self-assembled devices Electricity 0 Active
US12150297B2 Thin film transistors having a backside channel contact for high density memory Electricity 0 Active
US11594448B2 Vertical edge blocking (VEB) technique for increasing patterning process margin Electricity 0 Active
US12278204B2 Pattern decomposition lithography techniques Electricity 0 Active
US11950407B2 Memory architecture with shared bitline at back-end-of-line Electricity 0 Active
US12148734B2 Transistors, memory cells, and arrangements thereof Electricity 0 Active
US11581412B2 Contact over active gate structures with conductive gate taps for advanced integrated circuit structure fabrication Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.