Vertical memory device
US10204919B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2016 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Nov 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.