Semiconductor device and manufacturing method of the same
US10204980B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 23, 2017 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Jun 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0291
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include an element region and a peripheral voltage withstanding region. The peripheral voltage withstanding region includes inner circumferential guard rings; and outer circumferential guard rings having a width narrower than a width of the inner circumferential guard rings. An interval between the inner circumferential guard rings is narrower than an interval between the outer circumferential guard rings. Each of the inner circumferential guard rings includes a first high concentration region and a first low concentration region. Each of the outer circumferential guard rings includes a second high concentration region and a second low concentration region. A width of a part of each first low concentration region that is exposed on a front surface of the semiconductor device is wider than a width of a part of each second low concentration region that is exposed on the front surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.