Metal-oxide-semiconductor transistor and method of forming gate layout
US10204996B2 · kind B2 · utility
2Cited by
3References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 4, 2017 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Oct 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.