Method for manufacturing an integrated circuit including a lateral trench transistor and a logic circuit element

US10205016B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Andreas Meiser · Unterhaching, DE
• Till Schloesser · Dresden, DE
• Detlef Weber · Grünberg, DE
• Karl-Heinz Gebhardt · Dresden, DE

Key dates

• Filing date: Apr 11, 2017
• Grant date: Feb 12, 2019
• Expiry date: Apr 11, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/856
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.