Semiconductor memory device
US10205090B2 · kind B2 · utility
2Cited by
7References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2017 |
| Grant date | Feb 12, 2019 |
| Priority date | — |
| Expiry date | Feb 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
A semiconductor memory device that includes at least a lower contact plug on a semiconductor substrate, a magnetic tunnel junction of the lower contact plug, and a barrier pattern on a sidewall of the lower contact plug may further include an insulation pattern on the sidewall of the lower contact plug. The insulation pattern may be between the barrier pattern and the magnetic tunnel junction pattern. The insulation pattern may include an upper portion and a lower portion whose width is greater than a width of the upper portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.