Patent · US Active

Clock duty cycle correction circuit

US10205445B1 · kind B1 · utility

4Cited by

15References

19Claims

0Family size

Assignee

SYNOPSYS, INC. · US

Inventors

Shourya Kansal · Bengaluru, IN
Biman Chattopadhyay · Savanuru, IN
Ravi Mehta · Savanuru, IN
Jayesh Wadekar · Ashti, IN

Key dates

Filing date	Jan 4, 2018
Grant date	Feb 12, 2019
Priority date	—
Expiry date	Jan 4, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/1565
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A duty cycle correction (DCC) circuit includes first and second pluralities of logic gates, a low pass filter, an error amplifier, and a differential amplifier. The DCC circuit receives first and second clock signals from the VCO. The first and second pluralities of logic gates receive first and second superimposed clock signals and generate first and second output clock signals, respectively. The error amplifier rectifies a common error of the first and second output clock signals, and generates a common mode error voltage signal. The differential amplifier generates first and second error signals based on the common mode error voltage signal. The first and second error signals converge the duty cycles of the first and second output clock signals to a 50% duty cycle.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.