Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions
US10209995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2014 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Aug 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core supporting out-of-order execution (OOE) includes load-hit-store (LHS) hazard prediction at the instruction execution phase, reducing load instruction rejections and queue flushes at the dispatch phase. The instruction dispatch unit (IDU) detects likely LHS hazards by generating entries for pending stores in a LHS detection table. The entries in the table contain an address field (generally the immediate field) of the store instruction and the register number of the store. The IDU compares the address field and register number for each load with entries in the table to determine if a likely LHS hazard exists and if an LHS hazard is detected, the load is dispatched to the issue queue of the load-store unit (LSU) with a tag corresponding to the matching store instruction, causing the LSU to dispatch the load only after the corresponding store has been dispatched for execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.