Inventor · Austin, TX, US

Sundeep Chadha

81Patents
6h-index
72Co-inventors
75Inventor score

Filing activity: May 15, 2003 → May 4, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US7080269B2 Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains Emerging Cross-Sectional Technologies 15 Expired
US9367322B1 Age based fast instruction issue Physics 14 Active
US7051299B2 Method for generating reusable behavioral code Physics 10 Expired
US9983875B2 Operation of a multi-slice processor preventing early dependent instruction wakeup Physics 8 Active
US10037229B2 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions Physics 6 Active
US10042770B2 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions Physics 6 Active
US7882278B2 Utilizing programmable channels for allocation of buffer space and transaction control in data communications Physics 6 Active
US7493426B2 Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction control Physics 5 Expired
US9928128B2 In-pipe error scrubbing within a processor core Physics 5 Active
US10209995B2 Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions Physics 5 Active
US7761825B2 Generating testcases based on numbers of testcases previously generated Physics 4 Active
US9740620B2 Distributed history buffer flush and restore handling in a parallel slice design Physics 4 Active
US7853420B2 Performing temporal checking Physics 3 Active
US9747217B2 Distributed history buffer flush and restore handling in a parallel slice design Physics 3 Active
US10223125B2 Linkable issue queue parallel execution slice processing method Physics 3 Active
US9389870B1 Age based fast instruction issue Physics 3 Active
US7502966B2 Testcase generation via a pool of parameter files Physics 2 Active
US7516430B2 Generating testcases based on numbers of testcases previously generated Physics 2 Expired
US10133581B2 Linkable issue queue parallel execution slice for a processor Physics 2 Active
US9959121B2 Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers Physics 2 Active
US9389867B2 Speculative finish of instruction execution in a processor core Physics 2 Active
US7464354B2 Method and apparatus for performing temporal checking Physics 2 Active
US9921833B2 Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor Physics 2 Active
US9286068B2 Efficient usage of a multi-level register file utilizing a register file bypass Physics 2 Active
US11163571B1 Fusion to enhance early address generation of load instructions in a microprocessor Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.