Multi-stage address translation for a computing device
US10210096B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2013 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Feb 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (TLB) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors. The memory management controller includes logic configured for caching virtual address to physical address translations and intermediate physical address to physical address translations in the shared TLB, logic configured to receive a virtual address for translation from a requester, logic configured to conduct a table walk of a translation table in the shared TLB to determine a translated physical address in accordance with the virtual address, and logic configured to transmit the translated physical address to the requester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.