Ampere Computing LLC
68Patents
68Active
68Granted
66Portfolio score
Filing activity: Mar 15, 2013 → May 29, 2024
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10348281B1 | Clock control based on voltage associated with a microprocessor | Electricity | 13 | Active |
| US9928183B2 | Priority framework for a computing device | Emerging Cross-Sectional Technologies | 9 | Active |
| US10162373B1 | Variation immune on-die voltage droop detector | Electricity | 9 | Active |
| US10318696B1 | Efficient techniques for process variation reduction for static timing analysis | Physics | 5 | Active |
| US10318676B2 | Techniques for statistical frequency enhancement of statically timed designs | Physics | 4 | Active |
| US10145868B2 | Self-referenced on-die voltage droop detector | Physics | 4 | Active |
| US9971693B2 | Prefetch tag for eviction promotion | Physics | 2 | Active |
| US10205666B2 | End-to-end flow control in system on chip interconnects | Electricity | 2 | Active |
| US12019565B2 | Advanced initialization bus (AIB) | Physics | 2 | Active |
| US9965419B1 | Multiple-queue integer coalescing mapping algorithm with shared based time | Physics | 2 | Active |
| US11880686B2 | Devices transferring cache lines, including metadata on external links | Physics | 1 | Active |
| US10083131B2 | Generating and/or employing a descriptor associated with a memory translation table | Physics | 1 | Active |
| US10210096B2 | Multi-stage address translation for a computing device | Physics | 1 | Active |
| US10191868B2 | Priority framework for a computing device | Emerging Cross-Sectional Technologies | 1 | Active |
| US11934263B2 | Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization | Physics | 1 | Active |
| US10339065B2 | Optimizing memory mapping(s) associated with network nodes | Physics | 0 | Active |
| US10102164B2 | Multiple-queue integer coalescing mapping algorithm with shared based time | Physics | 0 | Active |
| US10109345B2 | Write assist for memories with resistive bit lines | Electricity | 0 | Active |
| US12175243B2 | Hardware micro-fused memory operations | Physics | 0 | Active |
| US12204410B2 | Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilization | Physics | 0 | Active |
| US11822487B2 | Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer | Physics | 0 | Active |
| US11977638B2 | Low-impact firmware update | Physics | 0 | Active |
| US12141587B2 | Generalized boot operation for disaggregated, multiple (multi-) die computing systems, and related methods | Physics | 0 | Active |
| US11868209B2 | Method and system for sequencing data checks in a packet | Physics | 0 | Active |
| US10049725B2 | Write assist for memories with resistive bit lines | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.