Synchronous data input/output system using prefetched device table entry
US10210131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2016 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Feb 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments include methods, systems, and computer program products for performing synchronous data I/O. Aspects include a processor of computer system sending a store block to request data from a device through a PCIe connection, requested data having a predetermined number of data blocks, and the processor executing a data transaction loop to retrieve requested data. Executing the data transaction loop may include writing to a table prefetch trigger register on host bridge to queue up speculative prefetches in ETU for each data block. The host bridge may perform a first speculative prefetch to install a device table entry in a device table cache. The processor may further perform a second speculative prefetch to install an address translation in an address translation cache. The host bridge processes the data block received through direct memory access over the PCIe connection using the prefetched device table entry and address translation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.