Electrostatic damage protection circuitry verification
US10210302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2016 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Jan 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to or beyond the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.