Associative row decoder
US10210935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Dec 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple instruction, multiple data memory device includes a memory array with several sections, one or more multiplexers between the sections and a decoder. Each section has memory cells arranged in rows and columns. The cells in a row are connected by a read enabled word line and by a write enabled word line. The decoder includes a decoder memory array which generally simultaneously activates a plurality of read enabled word lines in several sections, a plurality of write enabled word lines in several sections and one or more multiplexers. The decoder memory array includes several bit lines oriented perpendicularly to and connected to the rows of the memory array. A method of activating in-memory computation using several bit lines of a decoder memory array, connected to rows of the memory array to simultaneously activate several read enabled word lines, several write enabled word lines and one or more multiplexers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.