Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects
US10211088B2 · kind B2 · utility
9Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2015 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Sep 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.