Gate structures and fabrication methods thereof
US10211108B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 10, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Aug 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor structure includes forming a plurality of dummy gate structures on a substrate. Each dummy gate structure includes a gate dielectric layer, a dummy gate electrode, and two sidewall spacers. The method also includes forming a dielectric layer on the substrate between neighboring dummy gate structures and removing a portion of each dummy gate electrode to form a first opening. The first opening is surrounded by a remaining portion of the dummy gate electrode and the two sidewall spacers. The method further includes removing a portion of each sidewall spacer along a direction perpendicular to the sidewall of the first opening to form a second opening, removing the remaining portion of the gate electrode on the bottom of each second opening to form a third opening, and then filling each third opening with a gate electrode material to form a gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.