Packaged semiconductor device having multi-level leadframes configured as modules
US10211132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2018 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Mar 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A leadframe (100) comprises a frame (101) of sheet metal in a first planar level, where the frame has metallic leads (110) and a first metallic pad (120) extending inward from the frame, and the first pad is tied to the frame by first metallic straps (120a). The leadframe further has a second metallic pad (130) in a second planar level parallel to and spaced from the first level, where the second pad is tied by second metallic straps (132) to the frame. In addition, the leadframe has a third metallic pad (140) in a third planar level parallel to and spaced from the second level and additively from the first level, where the third pad is tied by third metallic straps (131) to the second pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.