Semiconductor device
US10211220B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Aug 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.