Vertical ferroelectric memory device and a method for manufacturing thereof
US10211223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2015 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Feb 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same. In one aspect, a vertical ferroelectric memory device includes a stack of horizontal layers formed on a semiconductor substrate, where the stack of layers includes a plurality gate electrode layers alternating with a plurality of insulating layers. A vertical structure extends vertically through the stack of horizontal layers, where the vertical structure has a vertical channel structure and a sidewall having formed thereon a vertical transition metal oxide (TMO) ferroelectric layer. A memory cell is formed at each of overlapping regions between the gate electrode layers and the vertical channel structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.