Semiconductor heterostructures and methods for forming same
US10211297B2 · kind B2 · utility
2Cited by
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21Claims
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Assignee
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Key dates
| Filing date | May 3, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | May 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/854
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A heterostructure includes a substrate; an intermediate layer disposed on the substrate; and a group III-V layer having a first primary surface disposed on the intermediate layer and a dopant concentration that varies in a manner including a plurality of ramps with at least one of increasing dopant concentration and decreasing dopant concentration, along the growth direction from the first primary surface throughout the layer's thickness before terminating in a second primary surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.