Method for combining NVM class and SRAM class MRAM elements on the same chip
US10211395B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Dec 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F10/3286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a magnetic random access memory chip having magnetic memory elements with different performance characteristics formed on the same chip. The magnetic memory elements can be magnetic random access memory elements. The memory chip can have a first set of magnetic random access chips having a first set of physical and performance characteristics formed in a first area of the sensor and a second set of magnetic random access chips having a second set of performance characteristics formed in a second area of the chip. For example, the first set of magnetic random access memory elements can have performance characteristics that match or exceed those of a non-volatile memory, whereas the second set of magnetic random access memory elements can have performance characteristic that match or exceed those of a static random access memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.