Digital low drop-out regulator and operation method thereof
US10216209B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 11, 2018 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Jun 11, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A digital Low Drop-Out regulator includes: an event-driven circuit for generating a trigger signal by asynchronously detecting whether an output voltage is out of a threshold range to generate a first error information signal and a first control signal; a time-driven circuit for generating a second error information signal by detecting a change in the output voltage synchronized with a clock signal, and generating a second control signal by combining the first and second error information signals; a clock/trigger control circuit for generating the clock signal having a first or second cycle based on the trigger signal and the first and second error information signals; a first array driver for controlling driving force of the output voltage in response to the first control signal; and a second array driver for controlling the driving force of the output voltage in response to the second control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.