Refreshing of dynamic random access memory
US10216658B2 · kind B2 · utility
1Cited by
4References
14Claims
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Key dates
| Filing date | May 19, 2017 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Jul 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10159
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. A microcontroller uses a counter to count how many times a rank of the DRAM is refreshed entirely (whether by a one-time per-rank refresh operation or by a series of per-bank refresh operations). When the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue, the microcontroller repeatedly performs the per-rank refresh operation on the rank. Every refresh inspection interval, the microcontroller decreases the counter by 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.