Permuting in a matrix-vector processor
US10216705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2018 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Apr 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.