Systems and methods for power efficient flop clustering
US10216880B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2016 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Nov 11, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems of optimization of and Integrated Circuit (IC) design disclosed herein result in a power efficient clustering of circuit devices. The methods may depart from the conventional geometric clustering using a nearest neighbor approach when wiring flops to local clock buffers. To reduce the number of clock-gaters, the methods in one embodiment use a grouping of flops wired to a common clock-gater to form nodes, which are then wired to the local clock buffers based on a load-balancing process. In another embodiment, the methods use a local cleanup process to rewire the nodes between neighboring clock buffers to further reduce the amount of clock-gaters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.