Inventor · Cedar Park, TX, US

Charles J. Alpert

119Patents

15h-index

91Co-inventors

89Inventor score

Filing activity: Sep 15, 1997 → Jul 5, 2023

Most-cited inventions

Patent	Title	Area	Cited by	Status
US6117182A	Optimum buffer placement for noise avoidance	Physics	213	Expired
US6347393B1	Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation	Physics	212	Expired
US6401234B1	Method and system for re-routing interconnects within an integrated circuit design having blockages and bays	Physics	95	Expired
US7065730B2	Porosity aware buffered steiner tree construction	Physics	89	Expired
US6996512B2	Practical methodology for early buffer and wire resource allocation	Physics	46	Expired
US7549137B2	Latch placement for high performance and low power circuits	Physics	37	Active
US7624366B2	Clock aware placement	Physics	22	Active
US8677299B1	Latch clustering with proximity to local clock buffers	Physics	20	Active
US6044209A	Method and system for segmenting wires prior to buffer insertion	Physics	19	Expired
US8495548B2	Multi-patterning lithography aware cell placement in integrated circuit design	Emerging Cross-Sectional Technologies	18	Active
US7127696B2	Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management	Physics	17	Expired
US6591411B2	Apparatus and method for determining buffered steiner trees for complex circuits	Emerging Cross-Sectional Technologies	16	Expired
US8954912B2	Structured placement of latches/flip-flops to minimize clock power in high-performance designs	Physics	16	Active
US7299442B2	Probabilistic congestion prediction with partial blockages	Physics	16	Expired
US8793636B2	Placement of structured nets	Physics	15	Active
US6671867B2	Analytical constraint generation for cut-based global placement	Physics	14	Expired
US6915361B2	Optimal buffered routing path constructions for single and multiple clock domains systems	Physics	14	Expired
US7934188B2	Legalization of VLSI circuit placement with blockages using hierarchical row slicing	Physics	13	Active
US8010926B2	Clock power minimization with regular physical placement of clock repeater components	Physics	11	Active
US7296252B2	Clustering techniques for faster and better placement of VLSI circuits	Physics	11	Expired
US7895557B2	Concurrent buffering and layer assignment in integrated circuit layout	Physics	10	Active
US8667441B2	Clock optimization with local clock buffer control optimization	Physics	10	Active
US7707530B2	Incremental timing-driven, physical-synthesis using discrete optimization	Physics	10	Active
US7073144B2	Stability metrics for placement to quantify the stability of placement algorithms	Physics	10	Expired
US7020861B2	Latch placement technique for reduced clock signal skew	Physics	9	Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.