Method for processing interconnection structure for minimizing barrier sidewall recess
US10217662B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2015 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Aug 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for processing an interconnection structure for minimizing barrier sidewall recess, comprises the following steps: step 1, remove a metal layer (408) to generate a uniform dishing value inside the recessed area (409), the uniform dishing value is generated to make sure that the top surface of the metal layer (408) in the recessed area (409) is aligned with the bottom surface of the hard mask layer (405), step 2, introduce noble-gas-halogen compound gas to remove a first barrier layer (406) on top surface and at least a portion of a second barrier layer (407) on sidewall by a gas phase chemical reaction process, the top surface of the second barrier layer (407) on sidewall is aligned with the bottom surface of the hard mask layer (405), step 3, introduce oxidizing gas to generate a barrier surface oxide (411) on the top surface of the second barrier layer (407) on sidewall, a metal surface oxide (412) is generated at the same time, step 4, introduce noble-gas-halogen compound gas to remove hard mask layer (405) by a gas phase chemical reaction process, step 5, reduce or remove the metal surface oxide (412).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.