3D semiconductor device, fabrication method and system
US10217667B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2018 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Feb 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.