Stacked semiconductor dies including inductors and associated methods
US10217726B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. In some embodiments, a semiconductor device comprises a substrate, a first die mounted to the substrate and including first inductors, and a second die mounted to the first die in an offset position and including second inductors. The first inductors are at an active side of the first die, and the second inductors are at an active side of the second die. At least a portion of the first inductors are proximate and inductively coupled to the second inductors. The semiconductor device further comprises a first plurality of interconnects electrically coupling the substrate to the first die, and a second plurality of interconnects electrically coupling the second die to the substrate. The first plurality of interconnects extend from an upper surface of the substrate to the active side of the first die, and the second plurality of interconnects extend from the active side of the second die to the lower surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.