Manufacturing method of semiconductor memory device
US10217749B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 13, 2018 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Feb 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate having a memory cell region and a peripheral region defined thereon is provided. Bit line structures are formed on the memory cell region. At least one gate structure is formed on the peripheral region. A spacer layer is formed covering the semiconductor substrate, the gate structure, and the bit line structures. The spacer layer is partly disposed on the memory cell region and partly disposed on the peripheral region. A first etching process is performed to the spacer layer for removing a part of the spacer layer on the memory cell region. At least a part of the spacer layer remains on the memory cell region after the first etching process. A second etching process is performed after the first etching process for removing the spacer layer remaining on the memory cell region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.