Method for fabricating semiconductor device
US10217756B2 · kind B2 · utility
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14References
7Claims
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Key dates
| Filing date | Apr 11, 2018 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Jun 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.