Gain calibration for ADC with external reference
US10218377B2 · kind B2 · utility
5Cited by
8References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 6, 2016 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Jul 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/466
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.