Generating physically aware network-on-chip design from a physical system-on-chip specification
US10218580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2015 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Nov 30, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S40/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Different example implementations of the present disclosure relates to methods and computer readable mediums for automatically generating physically aware NoC design and physically aware NoC Specification based on one or more of given SoC architectural details, physical information of SoC, traffic specification, power profile and one or more constraints. The method includes steps of receiving input information, determining the location/position of different NoC agents, interconnecting channels, pins, I/O interfaces, physical/virtual boundaries, number of layers, size/depth/width of different channels at different time, and locating/configuring the different NoC agents, interconnecting channels, pins, I/O interfaces, and physical/virtual boundaries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.