Inventor · San Jose, CA, US

Sailesh Kumar

95Patents
23h-index
38Co-inventors
84Inventor score

Filing activity: Jun 9, 2008 → Jul 7, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8601423B1 Asymmetric mesh NoC topologies Electricity 92 Active
US8667439B1 Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost Physics 87 Active
US8819611B2 Asymmetric mesh NoC topologies Electricity 55 Active
US9568970B1 Hardware and software enabled implementation of power profile management instructions in system on chip Emerging Cross-Sectional Technologies 52 Active
US9444702B1 System and method for visualization of NoC performance based on simulation output Electricity 51 Active
US9223711B2 Combining associativity and cuckoo hashing Physics 44 Active
US9571341B1 Clock gating for system-on-chip elements Emerging Cross-Sectional Technologies 34 Active
US9529400B1 Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements Emerging Cross-Sectional Technologies 32 Active
US8885510B2 Heterogeneous channel capacities in an interconnect Electricity 29 Active
US9699079B2 Streaming bridge design with host interfaces and network on chip (NoC) layers Electricity 28 Active
US9473388B2 Supporting multicast in NOC interconnect Electricity 27 Active
US9571402B2 Congestion control and QoS in NoC by regulating the injection traffic Electricity 26 Active
US9477280B1 Specification for automatic power management of network-on-chip and system-on-chip Emerging Cross-Sectional Technologies 26 Active
US9244880B2 Automatic construction of deadlock free interconnects Electricity 26 Active
US9590813B1 Supporting multicast in NoC interconnect Electricity 26 Active
US9244845B2 System and method for improving snoop performance Physics 25 Active
US9294354B2 Using multiple traffic profiles to design a network on chip Physics 25 Active
US9535848B2 Using cuckoo movement for improved cache coherency Physics 24 Active
US9473415B2 QoS in a system with end-to-end flow control and QoS aware buffer allocation Electricity 24 Active
US9473359B2 Transactional traffic specification for network-on-chip design Electricity 24 Active
US9471726B2 System level simulation in network on chip architecture Physics 24 Active
US9569579B1 Automatic pipelining of NoC channels to meet timing and/or performance Physics 23 Active
US9319232B2 Integrated NoC for performing data communication and NoC functions Electricity 23 Active
US9571420B2 Integrated NoC for performing data communication and NoC functions Electricity 22 Active
US9253085B2 Hierarchical asymmetric mesh with virtual routers Electricity 22 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.